As input/output (I/O) buffers become more complicated in design, optimizing and/or debugging the I/O systems for high volume manufacturing (HVM) becomes challenging. One possible reason for such challenge is that processors having modern I/O buffers are optimized to perform at a specific power consumption envelope for a fixed I/O voltage reference level. The voltage reference for the I/O system is used in the sense amplifiers of the receivers of the I/O buffers to determine the value of the incoming data. Generally, such voltage reference is set to a level which is a fraction of the I/O power supply, for example, ½ VCC or ⅔ VCC. Optimization of the I/O systems is then performed at those fixed I/O voltage reference levels. Optimization means setting the properties of the I/O buffers so that the I/O buffers operate in a particular power envelope, drive the I/O signals at a specific speed, maintain a certain timing margin for the I/O signals, operate within certain noise levels (crosstalk, overshoot, undershoot, ground bounce, ring back), etc.
However, improved and accurate optimization of an I/O buffer depends on the system in which the I/O buffer operates. This means that for every different type of I/O system, a different voltage reference level may be selected as its fixed voltage reference to achieve the optimized performance metrics of the I/O system. Such a customized fixed voltage reference increases the cost of HVM because it is expensive to change the fixed voltage reference to a new level for every different I/O system. Furthermore, the presence of the voltage reference generator off die on the motherboard requires special external cards to interface with the motherboard to override the fixed voltage reference level to a new level for I/O system optimization. Such external cards also increase the cost of HVM.
For example, a double data rate (DDR) interface of a Dynamic Random Access Memory (DRAM) operates with a fixed reference voltage for the DDR's Dual In-Line Memory Module (DIMM). Generally, the fixed reference voltage is set to ½ VCC level. Such fixed reference voltage is used by the DRAM to decide if the received data in its memory is a logical one or zero. Statically setting this voltage reference limits the ability to achieve the optimal DRAM operation point for a given I/O system. Such a fixed voltage reference also limits the ability to test DRAMs at HVM because external interface cards on the motherboards are needed to override fixed voltage reference levels for the DRAM sense amplifiers and to determine I/O system margins for various voltage reference levels.